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» Architectures for function evaluation on FPGAs
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ISCAS
2003
IEEE
112views Hardware» more  ISCAS 2003»
13 years 10 months ago
Architectures for function evaluation on FPGAs
This paper presents a new family of architectures for multi-cycle area-efficient evaluation of elementary and composite functions, and an exploration of the design tradeoffs for i...
Nalin Sidahao, George A. Constantinides, Peter Y. ...
FPGA
1998
ACM
146views FPGA» more  FPGA 1998»
13 years 9 months ago
Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation
In this paper, we developed Boolean matching techniques for complex programmable logic blocks (PLBs) in LUT-based FPGAs. A complex PLB can not only be used as a K-input LUT, but a...
Jason Cong, Yean-Yow Hwang
ASAP
2010
IEEE
193views Hardware» more  ASAP 2010»
13 years 6 months ago
Automatic generation of polynomial-based hardware architectures for function evaluation
Abstract--Polynomial approximation is a very general technique for the evaluation of a wide class of numerical functions of one variable. This article details an architecture gener...
Florent de Dinechin, Mioara Joldes, Bogdan Pasca
FPL
2004
Springer
93views Hardware» more  FPL 2004»
13 years 10 months ago
Second Order Function Approximation Using a Single Multiplication on FPGAs
Abstract. This paper presents a new scheme for the hardware evaluation of elementary functions, based on a piecewise second order minimax approximation. The novelty is that this ev...
Jérémie Detrey, Florent de Dinechin
FCCM
2002
IEEE
174views VLSI» more  FCCM 2002»
13 years 9 months ago
PAM-Blox II: Design and Evaluation of C++ Module Generation for Computing with FPGAs
This paper explores the implications of integrating flexible module generation into a compiler for FPGAs. The objective is to improve the programmabilityof FPGAs, or in other wor...
Oskar Mencer