67 search results - page 13 / 14 » Array-of-arrays architecture for parallel floating point mul... |
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been ide...
HPCA
2008
IEEE
14 years 6 months ago
2008
IEEE
We apply Amdahl's Law to multicore chips using symmetric cores, asymmetric cores, and dynamic techniques that allows cores to work together on sequential execution. To Amdahl...
ASPDAC
2007
ACM
13 years 10 months ago
2007
ACM
Logic synthesis has made impressive progress in the last decade and has pervaded digital design replacing almost universally manual techniques. A remarkable exception is computer ...
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
ECAI
2004
Springer
13 years 11 months ago
2004
Springer
In this paper we describe IPSS (Integrated Planning and Scheduling System), a domain independent solver that integrates an AI heuristic planner, that synthesizes courses of actions...