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» Asynchronous Design Using Commercial HDL Synthesis Tools
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ASYNC
2000
IEEE
181views Hardware» more  ASYNC 2000»
13 years 9 months ago
Asynchronous Design Using Commercial HDL Synthesis Tools
New design technologies rely on truly reusable IP blocks with simple means of assembly. Asynchronous methodologies could be a promising option to implement these requirements. Pro...
Michiel M. Ligthart, Karl Fant, Ross Smith, Alexan...
CHES
2006
Springer
205views Cryptology» more  CHES 2006»
13 years 8 months ago
Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks
Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite thei...
Konrad J. Kulikowski, Alexander B. Smirnov, Alexan...
ASPDAC
2001
ACM
127views Hardware» more  ASPDAC 2001»
13 years 8 months ago
High-level design for asynchronous logic
Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete High Le...
Ross Smith, Michiel M. Ligthart
DSD
2009
IEEE
88views Hardware» more  DSD 2009»
13 years 2 months ago
A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor
Abstract--The implementation of an efficient result forwarding unit for asynchronous processors faces the problem of the inherent lack of synchronisation between result producer an...
Luis A. Tarazona, Doug A. Edwards, Luis A. Plana
ICCAD
2002
IEEE
176views Hardware» more  ICCAD 2002»
14 years 1 months ago
High capacity and automatic functional extraction tool for industrial VLSI circuit designs
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
Sasha Novakovsky, Shy Shyman, Ziyad Hanna