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» Asynchronous Polycyclic Architecture

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ASYNC
1999
IEEE

100views Hardware» more ASYNC 1999»

RAPPID: An Asynchronous Instruction Length Decoder

13 years 10 months ago

Download www.csl.cornell.edu

This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID ("Revolving As...

Shai Rotem, Ken S. Stevens, Charles Dike, Marly Ro...

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ASYNC
2004
IEEE

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Static Tokens: Using Dataflow to Automate Concurrent Pipeline Synthesis

13 years 9 months ago

Download vlsi.cornell.edu

We describe a new intermediate compiler representation, static token form, that is suitable for dataflow-style synthesis of high-level asynchronous specifications. Static token fo...

John Teifel, Rajit Manohar

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ASPDAC
2011
ACM

215views Hardware» more ASPDAC 2011»

An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture

12 years 9 months ago

Download www.kameyama.ecei.tohoku.ac.jp

—This paper presents an asynchronous FPGA that combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. Four-phase dual-rail encoding is used for small...

Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama...

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DAC
2003
ACM

124views Computer Architecture» more DAC 2003»

Automating the design of an asynchronous DLX microprocessor

13 years 11 months ago