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ISCAS
2008
IEEE
102views Hardware» more  ISCAS 2008»
13 years 11 months ago
Asynchronous balanced gates tolerant to interconnect variability
Abstract— Existing methods of gate level power attack countermeasures depend on exact capacitance matching of the dual-rail data outputs of each gate. Process variability and a l...
Konrad J. Kulikowski, Vyas Venkataraman, Zhen Wang...
ASYNC
2007
IEEE
131views Hardware» more  ASYNC 2007»
13 years 11 months ago
High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link
A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67Gbps throughpu...
Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia...