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» Automated Bus Generation for Multiprocessor SoC Design
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MEMOCODE
2003
IEEE
13 years 10 months ago
LOTOS Code Generation for Model Checking of STBus Based SoC: the STBus interconnect
In the design process of SoC (System on Chip), validation is one of the most critical and costly activity. The main problem for industrial companies like STMicroelectronics, stand...
Pierre Wodey, Geoffrey Camarroque, Fabrice Baray, ...
DAC
2006
ACM
14 years 6 months ago
Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery
Modern integrated circuits (ICs) are becoming increasingly complex. The complexity makes it difficult to design, manufacture and integrate these high-performance ICs. The advent o...
Xinping Zhu, Wei Qin
DAC
2006
ACM
14 years 6 months ago
Programming models and HW-SW interfaces abstraction for multi-processor SoC
ing models and HW-SW Interfaces Abstraction for Multi-Processor SoC Ahmed A. Jerraya TIMA Laboratory 46 Ave Felix Viallet 38031 Grenoble CEDEX, France +33476574759 Ahmed.Jerraya@im...
Ahmed Amine Jerraya, Aimen Bouchhima, Fréd&...
DAC
2004
ACM
14 years 6 months ago
An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory
Massive data transfer encountered in emerging multimedia embedded applications requires architecture allowing both highly distributed memory structure and multiprocessor computati...
Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik...
DAC
2007
ACM
14 years 6 months ago
An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-based SoC Integration
The bus tracing is used to catch related signals for further investigation and analysis. However, the trace size of cycleaccurate tracing is large and the trace cycle is shallow u...
Chung-Fu Kao, Ing-Jer Huang, Chi-Hung Lin