9 search results - page 2 / 2 » Automated Incremental Synthesis of Timed Automata |
COMPSAC
2002
IEEE
13 years 10 months ago
2002
IEEE
Achievement of quality in software design, while never easy, is made more difficult by the inherent complexity of hard real-time (HRT) design. Furthermore, timing requirements in...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly impo...
CADE
2002
Springer
14 years 5 months ago
2002
Springer
Abstract. We investigate the combination of propositional SAT checkers with domain-specific theorem provers as a foundation for bounded model checking over infinite domains. Given ...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
Traditionally, rectilinear Steiner minimum trees (RSMT) are widely used for routing estimation in design optimizations like floorplanning and physical synthesis. Since it optimize...