6 search results - page 1 / 2 » Automated Multi-Cycle Symbolic Timing Verification of Microp... |
DAC
1994
ACM
13 years 8 months ago
1994
ACM
DAC
2000
ACM
14 years 5 months ago
2000
ACM
We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of fullcustom transistor-level circuit designs, and for the ...
DFG
2004
Springer
13 years 8 months ago
2004
Springer
This paper presents the real-time model checker RAVEN and related theoretical background. RAVEN augments the efficiency of traditional symbolic model checking with possibilities to...
DAC
2004
ACM
14 years 5 months ago
2004
ACM
ion of Assembler Programs for Symbolic Worst Case Execution Time Analysis Tobias Schuele Tobias.Schuele@informatik.uni-kl.de Klaus Schneider Klaus.Schneider@informatik.uni-kl.de Re...
LPAR
2010
Springer
13 years 2 months ago
2010
Springer
In automated synthesis, we transform a specification into a system that is guaranteed to satisfy the specification. In spite of the rich theory developed for temporal synthesis, l...