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ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
13 years 10 months ago
Partial scan delay fault testing of asynchronous circuits
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
Michael Kishinevsky, Alex Kondratyev, Luciano Lava...
VTS
1997
IEEE
105views Hardware» more  VTS 1997»
13 years 10 months ago
Critical hazard free test generation for asynchronous circuits
We describe a technique to generate critical hazard-free tests for self-timed control circuits build using a macromodule library, in a partial scan based DFT environment. Wepropos...
Ajay Khoche, Erik Brunvand
ITC
1994
IEEE
136views Hardware» more  ITC 1994»
13 years 9 months ago
An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms
Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza ...