Sciweavers

179 search results - page 3 / 36
» Automatic High Level Assertion Generation and Synthesis for ...
Sort
View
DATE
1998
IEEE
109views Hardware» more  DATE 1998»
13 years 9 months ago
Cross-Level Hierarchical High-Level Synthesis
This paper presents a new approach to cross-level hierarchical high-level synthesis. A methodology is presented, that supports the efficient synthesis of hierarchical specified sy...
Oliver Bringmann, Wolfgang Rosenstiel
RTCSA
2005
IEEE
13 years 11 months ago
Using UML 2.0 for System Level Design of Real Time SoC Platforms for Stream Processing
While enabling fast implementation and reconfiguration of stream applications, programmable stream processors expose issues of incompatibility and lack of adoption in existing st...
Yongxin Zhu, Zhenxin Sun, Alexander Maxiaguine, We...
KBSE
2006
IEEE
13 years 11 months ago
Model-driven Monitoring: Generating Assertions from Visual Contracts
The Visual Contract Workbench is a tool that supports model-driven development of software systems by lifting the Design by Contract idea, which is usually used at the code level,...
Marc Lohmann, Gregor Engels, Stefan Sauer
IESS
2007
Springer
143views Hardware» more  IESS 2007»
13 years 11 months ago
Embedded Software Development in a System-Level Design Flow
Abstract System level design is considered a major approach to tackle the complexity of modern System-on-Chip designs. Embedded software within SoCs is gaining importance as it add...
Gunar Schirner, Gautam Sachdeva, Andreas Gerstlaue...
ASPDAC
2009
ACM
139views Hardware» more  ASPDAC 2009»
14 years 1 days ago
Hardware-dependent software synthesis for many-core embedded systems
Abstract— This paper presents synthesis of Hardware Dependent Software (HdS) for multicore and many-core designs using Embedded System Environment (ESE). ESE is a tool set, devel...
Samar Abdi, Gunar Schirner, Ines Viskic, Hansu Cho...