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MICRO
2005
IEEE
136views Hardware» more  MICRO 2005»
13 years 10 months ago
Automatic Thread Extraction with Decoupled Software Pipelining
Until recently, a steadily rising clock rate and other uniprocessor microarchitectural improvements could be relied upon to consistently deliver increasing performance for a wide ...
Guilherme Ottoni, Ram Rangan, Adam Stoler, David I...
IEEEPACT
2007
IEEE
13 years 10 months ago
Speculative Decoupled Software Pipelining
In recent years, microprocessor manufacturers have shifted their focus from single-core to multi-core processors. To avoid burdening programmers with the responsibility of paralle...
Neil Vachharajani, Ram Rangan, Easwaran Raman, Mat...
CGO
2010
IEEE
13 years 11 months ago
Decoupled software pipelining creates parallelization opportunities
Decoupled Software Pipelining (DSWP) is one approach to automatically extract threads from loops. It partitions loops into long-running threads that communicate in a pipelined man...
Jialu Huang, Arun Raman, Thomas B. Jablin, Yun Zha...
CGO
2008
IEEE
13 years 11 months ago
Parallel-stage decoupled software pipelining
In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and ne...
Easwaran Raman, Guilherme Ottoni, Arun Raman, Matt...
MICRO
2007
IEEE
168views Hardware» more  MICRO 2007»
13 years 10 months ago
Global Multi-Threaded Instruction Scheduling
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...
Guilherme Ottoni, David I. August