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SAS
2010
Springer
262views Formal Methods» more  SAS 2010»
13 years 3 months ago
Concurrent Separation Logic for Pipelined Parallelization
Recent innovations in automatic parallelizing compilers are showing impressive speedups on multicore processors using shared memory with asynchronous channels. We have formulated a...
Christian J. Bell, Andrew W. Appel, David Walker
ASPDAC
2008
ACM
107views Hardware» more  ASPDAC 2008»
13 years 7 months ago
Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata
The information about the run-time behavior of software applications is crucial for enabling system level optimizations for embedded systems. This embedded Software Metadata inform...
Alexandros Bartzas, Miguel Peón Quiró...
CODES
2007
IEEE
13 years 11 months ago
A low power VLIW processor generation method by means of extracting non-redundant activation conditions
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuc...
MICRO
2007
IEEE
133views Hardware» more  MICRO 2007»
13 years 11 months ago
Revisiting the Sequential Programming Model for Multi-Core
Single-threaded programming is already considered a complicated task. The move to multi-threaded programming only increases the complexity and cost involved in software developmen...
Matthew J. Bridges, Neil Vachharajani, Yun Zhang, ...
DICS
2006
13 years 9 months ago
Fault-Tolerant Parallel Applications with Dynamic Parallel Schedules: A Programmer's Perspective
Dynamic Parallel Schedules (DPS) is a flow graph based framework for developing parallel applications on clusters of workstations. The DPS flow graph execution model enables automa...
Sebastian Gerlach, Basile Schaeli, Roger D. Hersch