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SAC
2002
ACM
13 years 4 months ago
Automatic code generation for executing tiled nested loops onto parallel architectures
This paper presents a novel approach for the problem of generating tiled code for nested for-loops using a tiling transformation. Tiling or supernode transformation has been widel...
Georgios I. Goumas, Maria Athanasaki, Nectarios Ko...
ICS
2009
Tsinghua U.
13 years 11 months ago
Parametric multi-level tiling of imperfectly nested loops
Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing da...
Albert Hartono, Muthu Manikandan Baskaran, C&eacut...
SAC
2004
ACM
13 years 10 months ago
Automatic parallel code generation for tiled nested loops
This paper presents an overview of our work, concerning a complete end-to-end framework for automatically generating message passing parallel code for tiled nested for-loops. It c...
Georgios I. Goumas, Nikolaos Drosinos, Maria Athan...
IPPS
2010
IEEE
13 years 2 months ago
DynTile: Parametric tiled loop generation for parallel execution on multicore processors
Abstract--Loop tiling is an important compiler transformation used for enhancing data locality and exploiting coarsegrained parallelism. Tiled codes in which tile sizes are runtime...
Albert Hartono, Muthu Manikandan Baskaran, J. Rama...
PPOPP
2009
ACM
14 years 5 months ago
Compiler-assisted dynamic scheduling for effective parallelization of loop nests on multicore processors
Recent advances in polyhedral compilation technology have made it feasible to automatically transform affine sequential loop nests for tiled parallel execution on multi-core proce...
Muthu Manikandan Baskaran, Nagavijayalakshmi Vydya...