16 search results - page 3 / 4 » Automatic code generation for executing tiled nested loops o... |
ICS
2009
Tsinghua U.
14 years 2 days ago
2009
Tsinghua U.
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
IEEEPACT
2009
IEEE
13 years 12 months ago
2009
IEEE
—Analytical models have been used to estimate optimal values for parameters such as tile sizes in the context of loop nests. However, important algorithms such as fast Fourier tr...
WCRE
2003
IEEE
13 years 10 months ago
2003
IEEE
Our research goal is to retarget image processing programs written in sequential languages (e.g., C) to architectures with data-parallel processing capabilities. Image processing ...
CASES
2009
ACM
13 years 11 months ago
2009
ACM
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalab...
CGO
2008
IEEE
13 years 11 months ago
2008
IEEE
In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and ne...