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ICCAD
2009
IEEE
179views Hardware» more  ICCAD 2009»
11 years 7 months ago
Automatic memory partitioning and scheduling for throughput and power optimization
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
Jason Cong, Wei Jiang, Bin Liu, Yi Zou
ISSS
1999
IEEE
89views Hardware» more  ISSS 1999»
12 years 1 months ago
Loop Scheduling and Partitions for Hiding Memory Latencies
Partition Scheduling with Prefetching (PSP) is a memory latency hiding technique which combines the loop pipelining technique with data prefetching. In PSP, the iteration space is...
Fei Chen, Edwin Hsing-Mean Sha
SIGCOMM
2010
ACM
11 years 9 months ago
EffiCuts: optimizing packet classification for memory and throughput
Packet Classification is a key functionality provided by modern routers. Previous decision-tree algorithms, HiCuts and HyperCuts, cut the multi-dimensional rule space to separate ...
Balajee Vamanan, Gwendolyn Voskuilen, T. N. Vijayk...
ISCA
2012
IEEE
234views Hardware» more  ISCA 2012»
9 years 12 months ago
PARDIS: A programmable memory controller for the DDRx interfacing standards
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
Mahdi Nazm Bojnordi, Engin Ipek
IPPS
2007
IEEE
12 years 3 months ago
A global address space framework for locality aware scheduling of block-sparse computations
In this paper, we present a mechanism for automatic management of the memory hierarchy, including secondary storage, in the context of a global address space parallel programming ...
Sriram Krishnamoorthy, Ümit V. Çataly&...
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