78 search results - page 2 / 16 » Automatic test generation using genetically-engineered disti... |
EDM
2009
13 years 2 months ago
2009
This paper describes a novel method to create a quantitative model of an educational content domain of related practice item-types using learning curves. By using a pairwise test t...
SIAMCOMP
2010
13 years 3 months ago
2010
Some systems interact with their environment at physically distributed interfaces, called ports, and in testing such a system it is normal to place a tester at each port. Each test...
ASE
2010
13 years 5 months ago
2010
Given a finite state machine M, a checking sequence is an input sequence that is guaranteed to lead to a failure if the implementation under test is faulty and has no more states t...
ATS
2009
IEEE
13 years 11 months ago
2009
IEEE
High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to faci...
RSP
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper addresses the need for formal specification and runtime verification of system-level requirements of distributed reactive systems. It describes a formalism for specifyi...