233 search results - page 2 / 47 » Balance Testing of Logic Circuits |
FPL
2000
Springer
13 years 9 months ago
2000
Springer
Abstract. In this paper we outline a procedure to determine appropriate partitioning of programmable logic and interconnect area to minimize overall device area across a broad rang...
ATS
2000
IEEE
13 years 10 months ago
2000
IEEE
Because domino logic design offers smaller area and faster delay than conventional CMOS design, it is very popular in the high-performance processor design. However, domino logic ...
KES
2005
Springer
13 years 11 months ago
2005
Springer
This paper presents a system for recognizing sketched logic circuits in real-time and graphically simulating them afterwords. It has been developed for use in university and school...
ITC
1995
IEEE
13 years 9 months ago
1995
IEEE
A nalog circuit implementations of fuzzy logic are characterized by performing logical connectives of analog signals. They can be considered as generalization of digital circuits ...
EURODAC
1990
IEEE
13 years 9 months ago
1990
IEEE
: In this paper logical cells and algorithms are presented supporting the design of pseudo-exhaustively testable circuits. The approach is based on real hardware segmentation, inst...