55 search results - page 3 / 11 » Balancing Logic Utilization and Area Efficiency in FPGAs |
VLSISP
2011
13 years 21 days ago
2011
This paper presents accurate area, time, power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family [1]. These models are designed to facilitate ef...
ICASSP
2008
IEEE
14 years 6 days ago
2008
IEEE
This paper presents accurate area and power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family. These models are designed to facilitate efficien...
GLVLSI
2009
IEEE
13 years 9 months ago
2009
IEEE
Recent technology mappers for LUT based FPGAs employ cut enumeration. Although many cuts are often needed to nd good network, enumerating all cuts with large size consumes run-tim...
FPGA
2000
ACM
13 years 9 months ago
2000
ACM
It has become clear that on-chip storage is an essential component of high-density FPGAs. These arrays were originally intended to implement storage, but recent work has shown tha...
EH
2004
IEEE
13 years 9 months ago
2004
IEEE
Field programmable gate arrays (FPGAs) are becoming increasingly important implementation platforms for digital circuits. One of the necessary requirements to effectively utilize ...