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ISPASS
2005
IEEE
10 years 9 months ago
Balancing Performance and Reliability in the Memory Hierarchy
Cosmic-ray induced soft errors in cache memories are becoming a major threat to the reliability of microprocessor-based systems. In this paper, we present a new method to accurate...
Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Ta...
SAC
2006
ACM
10 years 10 months ago
Operating system multilevel load balancing
This paper describes an algorithm that allows Linux to perform multilevel load balancing in NUMA computers. The Linux scheduler implements a load balancing algorithm that uses str...
Mônica Corrêa, Avelino Francisco Zorzo...
ASPLOS
2010
ACM
10 years 11 months ago
Dynamically replicated memory: building reliable systems from nanoscale resistive memories
DRAM is facing severe scalability challenges in sub-45nm technology nodes due to precise charge placement and sensing hurdles in deep-submicron geometries. Resistive memories, suc...
Engin Ipek, Jeremy Condit, Edmund B. Nightingale, ...
DAC
2006
ACM
11 years 5 months ago
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...
Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sh...
SAC
2004
ACM
10 years 9 months ago
Caching in Web memory hierarchies
Web cache replacement algorithms have received a lot of attention during the past years. Though none of the proposed algorithms deals efficiently with all the particularities of t...
Dimitrios Katsaros, Yannis Manolopoulos
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