3 search results - page 1 / 1 » Balancing the Interconnect Topology for Arrays of Processors... |
ICCD
2002
IEEE
14 years 1 months ago
2002
IEEE
High performance SoC requires nonblocking interconnections between an array of processors built on one chip. With the advent of deep sub-micron technologies, switches are becoming...
ICDT
2001
ACM
13 years 9 months ago
2001
ACM
This paper presents a general methodology for the efficient parallelization of existing data cube construction algorithms. We describe two different partitioning strategies, one f...
DATE
2010
IEEE
13 years 3 months ago
2010
IEEE
— Applications like 4G baseband modem require single-chip implementation to meet the integration and power consumption requirements. These applications demand a high computing pe...