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ISCAS
2005
IEEE
191views Hardware» more  ISCAS 2005»
13 years 10 months ago
Behavioural modeling and simulation of a switched-current phase locked loop
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
Peter R. Wilson, Reuben Wilcock
ASPDAC
2007
ACM
156views Hardware» more  ASPDAC 2007»
13 years 9 months ago
PLLSim - An Ultra Fast Bang-Bang Phase Locked Loop Simulation Tool
- This paper presents a simulation tool targeted specifically at bang-bang type phase locked loop systems. The aim of this simulator is to quickly and accurately predict important ...
Michael Chan, Adam Postula, Yong Ding
ICCD
2001
IEEE
88views Hardware» more  ICCD 2001»
14 years 1 months ago
Jitter-Induced Power/ground Noise in CMOS PLLs: A Design Perspective
CMOS Phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper...
Payam Heydari, Massoud Pedram