Sciweavers

15 search results - page 3 / 3
» Benchmark-based design strategies for single chip heterogene...
Sort
View
ASPLOS
2009
ACM
14 years 5 months ago
Accelerating critical section execution with asymmetric multi-core architectures
To improve the performance of a single application on Chip Multiprocessors (CMPs), the application must be split into threads which execute concurrently on multiple cores. In mult...
M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi...
ICDE
2006
IEEE
206views Database» more  ICDE 2006»
14 years 6 months ago
Query Co-Processing on Commodity Hardware
The rapid increase in the data volumes for the past few decades has intensified the need for high processing power for database and data mining applications. Researchers have acti...
Anastassia Ailamaki, Naga K. Govindaraju, Dinesh M...
ICPP
2009
IEEE
13 years 11 months ago
Bank-aware Dynamic Cache Partitioning for Multicore Architectures
Abstract—As Chip-Multiprocessor systems (CMP) have become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single c...
Dimitris Kaseridis, Jeffrey Stuecheli, Lizy K. Joh...
BMCBI
2010
175views more  BMCBI 2010»
13 years 4 months ago
Towards high performance computing for molecular structure prediction using IBM Cell Broadband Engine - an implementation perspe
Background: RNA structure prediction problem is a computationally complex task, especially with pseudo-knots. The problem is well-studied in existing literature and predominantly ...
S. P. T. Krishnan, Sim Sze Liang, Bharadwaj Veerav...
ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
13 years 4 months ago
Non-Inclusion Property in Multi-Level Caches Revisited
The center of gravity of computer architecture is moving toward memory systems. Barring breakthrough microarchitectural techniques to move processor performance to higher levels, ...
Mohamed M. Zahran, Kursad Albayraktaroglu, Manoj F...