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PACS
2004
Springer
102views Hardware» more  PACS 2004»
13 years 10 months ago
Bit-Sliced Datapath for Energy-Efficient High Performance Microprocessors
Sumeet Kumar, Prateek Pujara, Aneesh Aggarwal
ISCAS
2003
IEEE
103views Hardware» more  ISCAS 2003»
13 years 10 months ago
An ILP-based scheduling scheme for energy efficient high performance datapath synthesis
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
VLSID
2003
IEEE
92views VLSI» more  VLSID 2003»
14 years 5 months ago
Energy Efficient Scheduling for Datapath Synthesis
In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and re...
Saraju P. Mohanty, N. Ranganathan
ISLPED
2005
ACM
87views Hardware» more  ISLPED 2005»
13 years 10 months ago
Runtime identification of microprocessor energy saving opportunities
High power consumption and low energy efficiency have become significant impediments to future performance improvements in modern microprocessors. This paper contributes to the so...
W. L. Bircher, M. Valluri, J. Law, L. K. John
TVLSI
2010
12 years 12 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...