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» Boolean Matching Using Generalized Reed-Muller Forms
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DATE
2006
IEEE
145views Hardware» more  DATE 2006»
13 years 11 months ago
Building a better Boolean matcher and symmetry detector
Boolean matching is a powerful technique that has been used in technology mapping to overcome the limitations of structural pattern matching. The current basis for performing Bool...
Donald Chai, Andreas Kuehlmann
FPGA
2007
ACM
163views FPGA» more  FPGA 2007»
13 years 11 months ago
Improved SAT-based Boolean matching using implicants for LUT-based FPGAs
Boolean matching (BM) is a widely used technique in FPGA resynthesis and architecture evaluation. In this paper we present several improvements to the recently proposed SAT-based ...
Jason Cong, Kirill Minkovich
SAT
2004
Springer
106views Hardware» more  SAT 2004»
13 years 10 months ago
The Optimality of a Fast CNF Conversion and its Use with SAT
Despite the widespread use and study of Boolean satisfiability for a diverse range of problem domains, encoding of problems is usually given to general propositional logic with li...
Daniel Sheridan
ECAI
2006
Springer
13 years 8 months ago
A Solver for QBFs in Nonprenex Form
Various problems in AI can be solved by translating them into a quantified boolean formula (QBF) and evaluating the resulting encoding. In this approach, a QBF solver is used as a ...
Uwe Egly, Martina Seidl, Stefan Woltran
DAC
2009
ACM
14 years 5 months ago
Efficient SAT solving for non-clausal formulas using DPLL, graphs, and watched cuts
Boolean satisfiability (SAT) solvers are used heavily in hardware and software verification tools for checking satisfiability of Boolean formulas. Most state-of-the-art SAT solver...
Himanshu Jain, Edmund M. Clarke