19 search results - page 3 / 4 » Bounded Model Checking of Analog and Mixed-Signal Circuits U... |
DAC
2003
ACM
14 years 6 months ago
2003
ACM
We present an algorithm that checks behavioral consistency between an ANSI-C program and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the program ...
SPIN
2010
Springer
13 years 4 months ago
2010
Springer
Abstract. Context-Bounded Analysis has emerged as a practical automatic formal analysis technique for fine-grained, shared-memory concurrent software. Two recent papers (in CAV 20...
KBSE
2007
IEEE
13 years 12 months ago
2007
IEEE
A number of researchers have proposed the use of Boolean satisfiability solvers for verifying C programs. They encode correctness checks as Boolean formulas using finitization: ...
IFM
2009
Springer
14 years 4 days ago
2009
Springer
We present the new technique of dynamic path reduction (DPR), which allows one to prune redundant paths from the state space of a program under verification. DPR is a very general...
PEPM
2009
ACM
15 years 5 months ago
2009
ACM
The Verilog hardware description language has padding semantics that allow designers to write descriptions where wires of different bit widths can be interconnected. However, many ...