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DATE
2000
IEEE
142views Hardware» more  DATE 2000»
13 years 9 months ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi
ISQED
2007
IEEE
97views Hardware» more  ISQED 2007»
13 years 11 months ago
Probabilistic Congestion Prediction with Partial Blockages
— Fast and accurate routing congestion estimation is essential for optimizations such as floorplanning, placement, buffering, and physical synthesis that need to avoid routing c...
Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachi...
INFOCOM
1998
IEEE
13 years 9 months ago
Design of Logical Topologies: A Linear Formulation for Wavelength Routed Optical Networks with No Wavelength Changers
We consider the problem of constructing logical topologies over a wavelength-routed optical network with no wavelength changers. We present a general linear formulation which consi...
Rajesh M. Krishnaswamy, Kumar N. Sivarajan
DATE
2000
IEEE
169views Hardware» more  DATE 2000»
13 years 9 months ago
Transformational Placement and Synthesis
Novel methodology and algorithms to seamlessly integrate logic synthesis and physical placement through a transformational approach are presented. Contrary to most placement algor...
Wilm E. Donath, Prabhakar Kudva, Leon Stok, Paul V...
ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
14 years 2 months ago
Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems
Three dimensional vertically integrated systems allow active devices to be placed on multiple device layers. In recent years, a number of research efforts have addressed physical ...
Madhubanti Mukherjee, Ranga Vemuri