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» Branch Optimisation Techniques for Hardware Compilation
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SAMOS
2007
Springer
13 years 11 months ago
Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction
In this paper, we use the CoDeL hardware design platform to analyze the potential and performance impact of power gating individual registers. For each register, we examine the per...
Nainesh Agarwal, Nikitas J. Dimopoulos
ICCAD
1995
IEEE
110views Hardware» more  ICCAD 1995»
13 years 9 months ago
Fast functional simulation using branching programs
This paper addresses the problem of speeding up functional (delayindependent)logic simulation for synchronousdigital systems. The problem needs very little new motivation – cycl...
Pranav Ashar, Sharad Malik
AADEBUG
2005
Springer
13 years 11 months ago
Code coverage testing using hardware performance monitoring support
Code coverage analysis, the process of finding code exercised by a particular set of test inputs, is an important component of software development and verification. Most tradit...
Alex Shye, Matthew Iyer, Vijay Janapa Reddi, Danie...
HPCA
2007
IEEE
14 years 5 months ago
Improving Branch Prediction and Predicated Execution in Out-of-Order Processors
If-conversion is a compiler technique that reduces the misprediction penalties caused by hard-to-predict branches, transforming control dependencies into data dependencies. Althou...
Eduardo Quiñones, Joan-Manuel Parcerisa, An...
MICRO
1999
IEEE
110views Hardware» more  MICRO 1999»
13 years 9 months ago
Balance Scheduling: Weighting Branch Tradeoffs in Superblocks
Since there is generally insufficient instruction level parallelism within a single basic block, higher performance is achieved by speculatively scheduling operations in superbloc...
Alexandre E. Eichenberger, Waleed Meleis