27 search results - page 5 / 6 » Branch Optimisation Techniques for Hardware Compilation |
ISCA
1999
IEEE
13 years 9 months ago
1999
IEEE
Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
BMCBI
2010
13 years 4 months ago
2010
Background: Solving bioinformatics tasks often requires extensive computational power. Recent trends in processor architecture combine multiple cores into a single chip to improve...
CODES
2004
IEEE
13 years 8 months ago
2004
IEEE
The memory bandwidth largely determines the performance and energy cost of embedded systems. At the compiler level, several techniques improve the memory bandwidth at the scope of...
ICALP
2000
Springer
13 years 8 months ago
2000
Springer
Abstract. We describe SAFL, a call-by-value first-order functional language which is syntactically restricted so that storage may be statically allocated to fixed locations. Evalua...