4 search results - page 1 / 1 » Branch predictor guided instruction decoding |
IEEEPACT
2006
IEEE
13 years 11 months ago
2006
IEEE
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
MICRO
2002
IEEE
13 years 10 months ago
2002
IEEE
A value’s degree of use—the number of dynamic uses of that value—provides the most essential information needed to optimize its communication. We present simulation results ...
LCTRTS
2009
Springer
13 years 11 months ago
2009
Springer
Instruction fetch behavior has been shown to be very regular and predictable, even for diverse application areas. In this work, we propose the Lookahead Instruction Fetch Engine (...
ISCA
1999
IEEE
13 years 9 months ago
1999
IEEE
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet ...