69 search results - page 14 / 14 » Buffer insertion for clock delay and skew minimization |
INTEGRATION
2007
13 years 5 months ago
2007
The optimum wire shape to produce the minimum signal propagation delay across an RLC line is shown to exhibit a general exponential form. The line inductance makes exponential tap...
ATS
2000
IEEE
13 years 9 months ago
2000
IEEE
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
ICCAD
2004
IEEE
14 years 2 months ago
2004
IEEE
Wire pipelining emerges as a new necessity for global wires due to increasing wire delay, shrinking clock period and growing chip size. Existing approaches on wire pipelining are ...
DAC
1996
ACM
13 years 9 months ago
1996
ACM
: We presentdesign-for-low-power techniques based on glitch reduction for register-transfer level circuits. We analyze the generation and propagation of glitches in both the contro...