68 search results - page 14 / 14 » Buffered Crossbar Fabrics Based on Networks on Chip |
EUROPAR
2005
Springer
13 years 10 months ago
2005
Springer
Whereas the established interconnection networks (ICTN) achieve low latency by operating in the linear region, i.e. oversizing the fabric, the recent strict cost and power constrai...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
HPCA
2009
IEEE
14 years 5 months ago
2009
IEEE
Realizing scalable cache coherence in the many-core era comes with a whole new set of constraints and opportunities. It is widely believed that multi-hop, unordered on-chip networ...