Sciweavers

68 search results - page 2 / 14
» Buffered Crossbar Fabrics Based on Networks on Chip
Sort
View
CN
2006
99views more  CN 2006»
13 years 5 months ago
High-performance switching based on buffered crossbar fabrics
As buffer-less crossbar scheduling algorithms reach their practical limitations due to higher port numbers and data rates, internally buffered crossbar (IBC) switches have gained ...
Lotfi Mhamdi, Mounir Hamdi, Christopher Kachris, S...
HIPC
2003
Springer
13 years 10 months ago
Designing SANs to Support Low-Fanout Multicasts
Abstract. System area networks (SANs) need to support low-fanout multicasts efficiently in addition to broadcasts and unicasts. A critical component in SANs is the switch, which i...
Rajendra V. Boppana, Rajesh Boppana, Suresh Chalas...
ICC
2008
IEEE
126views Communications» more  ICC 2008»
13 years 11 months ago
Backlog Aware Scheduling for Large Buffered Crossbar Switches
—A novel architecture was proposed in [1] to address scalability issues in large, high speed packet switches. The architecture proposed in [1], namely OBIG (output buffers with i...
Aditya Dua, Benjamin Yolken, Nicholas Bambos, Wlad...
SIGCOMM
1995
ACM
13 years 8 months ago
Pipelined Memory Shared Buffer for VLSI Switches
ABSTRACT: Switch chips are building blocks for computer and communication systems. Switches need internal buffering, because of output contention; shared buffering is known to perf...
Manolis Katevenis, Panagiota Vatsolaki, Aristides ...
MICRO
2003
IEEE
99views Hardware» more  MICRO 2003»
13 years 10 months ago
Power-driven Design of Router Microarchitectures in On-chip Networks
As demand for bandwidth increases in systems-on-a-chip and chip multiprocessors, networks are fast replacing buses and dedicated wires as the pervasive interconnect fabric for on-...
Hangsheng Wang, Li-Shiuan Peh, Sharad Malik