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VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
Interconnect with an insufficient width may be subject to electromigration and eventually cause the failure of the circuit at any time during its lifetime. This problem has gotten...
ICCAD
1997
IEEE
13 years 9 months ago
1997
IEEE
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been...