40 search results - page 7 / 8 » Buffering Interconnect for Multicore Processor Designs |
ISCA
2008
IEEE
13 years 12 months ago
2008
IEEE
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...
WMPI
2004
ACM
13 years 11 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
SIES
2008
IEEE
13 years 11 months ago
2008
IEEE
—Chip multiprocessing design is an emerging trend for embedded systems. In this paper, we introduce a Java multiprocessor system-on-chip called JopCMP. It is a symmetric shared-m...
IPPS
2000
IEEE
13 years 9 months ago
2000
IEEE
The switch design for interconnection networks plays an important role in the overall performance of multiprocessors and computer networks. It is therefore crucial to study variou...
ANCS
2005
ACM
13 years 11 months ago
2005
ACM
This paper investigates the suitability of emerging tiled-architectures, equipped with low-latency on-chip networks, for high-performance network routing. In this paper, we presen...