Performance evaluation of a java chip-multiprocessor

—Chip multiprocessing design is an emerging trend for embedded systems. In this paper, we introduce a Java multiprocessor system-on-chip called JopCMP. It is a symmetric shared-memory multiprocessor and consists of up to 8 Java Optimized Processor (JOP) cores, an arbitration control device, and a global shared memory. All components are interconnected with a system-on-chip bus. This paper focuses on the performance evaluation of different hardware configurations of the multicore system. Therefore, we vary the instruction cache sizes, the number of processors and the memory bandwidth. Within our experiments, we measure the performance by running three benchmarks on real hardware: an embedded application from industry, a computationally intensive matrix multiplication and a synthetic benchmark that continuously accesses a shared data structure. Two different field-programmable gate arrays are used for the presented experiments. Our results illustrate the promises and limits of the pr...

• Type: Conference
• Year: 2008
• Where: SIES
• Authors: Christof Pitter, Martin Schoeberl
• Keywords: Embedded Systems, Java Multiprocessor System-on-chip, Memory Bandwidth, SIES 2008, Symmetric Shared-memory Multiprocessor