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» Building the functional performance model of a processor
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ISPASS
2006
IEEE
13 years 10 months ago
Automatic testcase synthesis and performance model validation for high performance PowerPC processors
The latest high-performance IBM PowerPC microprocessor, the POWER5 chip, poses challenges for performance model validation. The current stateof-the-art is to use simple hand-coded...
Robert H. Bell Jr., Rajiv R. Bhatia, Lizy K. John,...
VLSID
2000
IEEE
135views VLSI» more  VLSID 2000»
13 years 8 months ago
Performance and Functional Verification of Microprocessors
We address the problem of verifying the correctness of pre-silicon models of a microprocessor. We touch on the latest advances in this area by considering two different aspects of...
Pradip Bose, Jacob A. Abraham
ISCA
2007
IEEE
182views Hardware» more  ISCA 2007»
13 years 11 months ago
Configurable isolation: building high availability systems with commodity multi-core processors
High availability is an increasingly important requirement for enterprise systems, often valued more than performance. Systems designed for high availability typically use redunda...
Nidhi Aggarwal, Parthasarathy Ranganathan, Norman ...
HPCA
2006
IEEE
14 years 5 months ago
Construction and use of linear regression models for processor performance analysis
Processor architects have a challenging task of evaluating a large design space consisting of several interacting parameters and optimizations. In order to assist architects in ma...
P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthav...
SAC
2009
ACM
13 years 11 months ago
Building an efficient preference XML query processor
Today user-centered information acquisition over collections of complex XML documents is increasingly in demand. To this end, preferences have become an important paradigm enablin...
SungRan Cho, Wolf-Tilo Balke