74 search results - page 2 / 15 » Built-in test generation for synchronous sequential circuits |
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test applic...
ICCAD
1997
IEEE
13 years 9 months ago
1997
IEEE
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...
DSD
2005
IEEE
13 years 11 months ago
2005
IEEE
Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subta...
ATS
1997
IEEE
13 years 9 months ago
1997
IEEE
Testing circuits which do not include a global reset signal requires either complex ATPG algorithms based on 9- or even 256-valued algebras, or some suitable method to generate in...
VTS
1995
IEEE
13 years 8 months ago
1995
IEEE
In this paper, we propose an entirely new Built-In Self Test scheme for high-level synthesis of data path architectures that makes use of the arithmetic blocks in the data path to...