EURODAC 1995 - PDF Preprint Papers

EURODAC 1995 European Design Automation Conference with EURO-VHDL

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EURODAC
1995
IEEE

314views VHDL» more EURODAC 1995»

Procedure exlining: a new system-level specification transformation

13 years 8 months ago

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Frank Vahid

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Id	Views	Title	Status

1	314	Procedure exlining: a new system-level specification transformation	claim
2	294	A classification of design steps and their verification	claim
3	293	Functional-level analog macromodeling with piecewise linear signals	claim
4	202	Hardware-software co-synthesis of fault-tolerant real-time distributed embedded systems	claim
5	198	On generating compact test sequences for synchronous sequential circuits	claim
6	195	A hardware/software partitioning algorithm for pipelined instruction set processor	claim
7	182	Delay modelling improvement for low voltage applications	claim
8	180	Integration of VHDL into a system design environment	claim
9	173	Cooperative concurrency control for design environments	claim
10	164	Bottleneck removal algorithm for dynamic compaction and test cycles reduction	claim
11	162	ODE: output direct state machine encoding	claim
12	159	The VHDL based design of the MIDA MPEG1 audio decoder	claim
13	159	Timing constraint specification and synthesis in behavioral VHDL	claim
14	159	Performance-oriented placement and routing for field-programmable gate arrays	claim
15	156	VHDL quality: synthesizability, complexity and efficiency evaluation	claim
16	156	KANDIS - a tool for construction of mixed analog/digital systems	claim
17	155	Design and use of a system-level specification and verification methodology	claim
18	153	VHDL-based communication and synchronization synthesis	claim
19	152	Information model of a compound graph representation for system and architecture level design	claim
20	151	Model of conceptual design of complex electronic systems	claim
21	150	A reuse scenario for the VHDL-based hardware design flow	claim
22	149	Cosimulation of real-time control systems	claim
23	148	Software system for semiconductor devices, monolith and hybrid ICs thermal analysis	claim
24	146	Practical inter-operation of CAD tools using a flexible procedural interface	claim
25	142	Prediction of radiated electromagnetic emissions from PCB traces based on green dyadics	claim
26	142	Creating hierarchy in HDL-based high density FGPA design	claim
27	138	Reduced design time by load distribution with CAD framework methodology information	claim
28	137	A formal non-heuristic ATPG approach	claim
29	136	Computing subsets of equivalence classes for large FSMs	claim
30	135	A high performance VHDL simulator for large systems design	claim
31	134	Area efficient DSP datapath synthesis	claim
32	133	Tree restructuring approach to mapping problem in cellular-architecture FPGAs	claim
33	131	System level design, a VHDL based approach	claim
34	130	Scalable performance scheduling for hardware-software cosynthesis	claim
35	130	Semi-dynamic scheduling of synchronization-mechanisms	claim
36	128	Closeness metrics for system-level functional partitioning	claim
37	127	Layout synthesis for datapath designs	claim
38	126	Quality considerations in delay fault testing	claim
39	126	Towards verifying VHDL descriptions of processors	claim
40	126	Use of embedded scheduling to compile VHDL for effective parallel simulation	claim
41	126	Timing optimization by bit-level arithmetic transformations	claim
42	123	An approach for classification of integrated circuits by a knowledge conserving library concept	claim
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44	116	An improved relaxation approach for mixed system analysis with several simulation tools	claim
45	115	Verification of a production cell controller using symbolic timing diagrams	claim
46	112	On implementation choices for iterative improvement partitioning algorithms	claim
47	112	Post routing performance optimization via tapered link insertion and wiresizing	claim
48	107	A backplane approach for cosimulation in high-level system specification environments	claim
49	101	Exploiting power-up delay for sequential optimization	claim
50	100	A unified approach to the extraction of realistic multiple bridging and break faults	claim

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