10 search results - page 1 / 2 » C-Pack: A High-Performance Microprocessor Cache Compression ... |
DCC
2008
IEEE
13 years 6 months ago
2008
IEEE
Researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functional...
TVLSI
2010
12 years 11 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
GLOBECOM
2008
IEEE
13 years 4 months ago
2008
IEEE
Hash functions have a space complexity of O(n) and a possible time complexity of O(1). Thus, packet classifiers exploit hashing to achieve packet classification in wire speed. Esp...
PC
2007
13 years 4 months ago
2007
The Sony–Toshiba–IBM Cell Broadband Engine (Cell/B.E.) is a heterogeneous multicore architecture that consists of a traditional microprocessor (PPE) with eight SIMD co-process...
ICCD
2008
IEEE
14 years 1 months ago
2008
IEEE
—In this paper we examine techniques for increasing the effective bandwidth of the microprocessor offchip interconnect. We focus on mechanisms that are orthogonal to other techni...