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» CCC: Crossbar Connected Caches for Reducing Energy Consumpti...
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DSD
2003
IEEE
121views Hardware» more  DSD 2003»
13 years 10 months ago
CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors
With shrinking feature size of silicon fabrication technology, architects are putting more and more logic into a single die. While one might opt to use these transistors for build...
Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemi...
ISCA
2006
IEEE
123views Hardware» more  ISCA 2006»
13 years 4 months ago
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
Packet-based on-chip networks are increasingly being adopted in complex System-on-Chip (SoC) designs supporting numerous homogeneous and heterogeneous functional blocks. These Net...
Jongman Kim, Chrysostomos Nicopoulos, Dongkook Par...
MICRO
2010
IEEE
130views Hardware» more  MICRO 2010»
13 years 2 months ago
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
Minseon Ahn, Eun Jung Kim