15 search results - page 2 / 3 » Cache aware compression for processor debug support |
CASES
2001
ACM
13 years 8 months ago
2001
ACM
Abstract. Existing variable-length instruction formats provide higher code densities than fixed-length formats, but are ill-suited to pipelined or parallel instruction fetch and de...
ISCA
2009
IEEE
13 years 11 months ago
2009
IEEE
The advent of multicores has introduced new challenges for programmers to provide increased performance and software reliability. There has been significant interest in technique...
ISPDC
2010
IEEE
13 years 3 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
— The influence of interconnects on processor performance and cost is becoming increasingly pronounced with technology scaling. In this paper, we present a fast compression sche...
ISCA
2010
IEEE
13 years 10 months ago
2010
IEEE
Light-weight, flexible access control, which allows software to regulate reads and writes to any granularity of memory region, can help improve the reliability of today’s multi...