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» Cache oblivious stencil computations
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2009
ACM
14 years 7 days ago
A case for integrated processor-cache partitioning in chip multiprocessors
Existing cache partitioning schemes are designed in a manner oblivious to the implicit processor partitioning enforced by the operating system. This paper examines an operating sy...
Shekhar Srikantaiah, Reetuparna Das, Asit K. Mishr...
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
13 years 10 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 3 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt
ICDCS
1998
IEEE
13 years 9 months ago
Structuring Remote Object Systems for Mobile Hosts with Intermittent Connectivity
In distributed object systems, remote method inattempts to abstract communication between di erent machines to the level of object method invocation. Link failure in such systems ...
Girish Welling, Maximilian Ott
SPAA
2004
ACM
13 years 11 months ago
Cache-oblivious shortest paths in graphs using buffer heap
We present the Buffer Heap (BH), a cache-oblivious priority queue that supports Delete-Min, Delete, and Decrease-Key operations in O( 1 B log2 N B ) amortized block transfers fro...
Rezaul Alam Chowdhury, Vijaya Ramachandran