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PLDI
1999
ACM
13 years 8 months ago
Cache-Conscious Structure Layout
Hardware trends have produced an increasing disparity between processor speeds and memory access times. While a variety of techniques for tolerating or reducing memory latency hav...
Trishul M. Chilimbi, Mark D. Hill, James R. Larus
COMPUTER
2000
138views more  COMPUTER 2000»
13 years 4 months ago
Making Pointer-Based Data Structures Cache Conscious
Processor and memory technology trends portend a continual increase in the relative cost of accessing main memory. Machine designers have tried to mitigate the effect of this tren...
Trishul M. Chilimbi, Mark D. Hill, James R. Larus
IPPS
2000
IEEE
13 years 9 months ago
Dynamic Data Layouts for Cache-Conscious Factorization of DFT
Effective utilization of cache memories is a key factor in achieving high performance in computing the Discrete Fourier Transform (DFT). Most optimizationtechniques for computing ...
Neungsoo Park, Dongsoo Kang, Kiran Bondalapati, Vi...
ACSC
2007
IEEE
13 years 11 months ago
HAT-Trie: A Cache-Conscious Trie-Based Data Structure For Strings
Tries are the fastest tree-based data structures for managing strings in-memory, but are space-intensive. The burst-trie is almost as fast but reduces space by collapsing trie-cha...
Nikolas Askitis, Ranjan Sinha
SPIRE
2005
Springer
13 years 10 months ago
Cache-Conscious Collision Resolution in String Hash Tables
In-memory hash tables provide fast access to large numbers of strings, with less space overhead than sorted structures such as tries and binary trees. If chains are used for collis...
Nikolas Askitis, Justin Zobel