Cache-Conscious Structure Layout

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Cache-Conscious Structure Layout
Hardware trends have produced an increasing disparity between processor speeds and memory access times. While a variety of techniques for tolerating or reducing memory latency have been proposed, these are rarely successful for pointer-manipulating programs. This paper explores a complementary approach that attacks the source (poor reference locality) of the problem rather than its manifestation (memory latency). It demonstrates that careful data organization and layout provides an essential mechanism to improve the cache locality of pointer-manipulating programs and consequently, their performance. It explores two placement techniques—clustering and coloring—that improve cache performance by increasing a pointer structure’s spatial and temporal locality, and by reducing cache-conflicts. To reduce the cost of applying these techniques, this paper discusses two strategies—cache-conscious reorganization and cacheconscious allocation—and describes two semi-automatic tools— cc...
Trishul M. Chilimbi, Mark D. Hill, James R. Larus
Added 03 Aug 2010
Updated 03 Aug 2010
Type Conference
Year 1999
Where PLDI
Authors Trishul M. Chilimbi, Mark D. Hill, James R. Larus
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