473 search results - page 3 / 95 » Cache-Conscious Structure Layout |
IEEEPACT
2009
IEEE
13 years 3 months ago
2009
IEEE
As the gap between processor and memory continues to grow, memory performance becomes a key performance bottleneck for many applications. Compilers therefore increasingly seek to m...
PAMI
2000
13 years 5 months ago
2000
TOG
2012
11 years 8 months ago
2012
We present a theoretical framework and practical method for the automatic construction of simple, all-quadrilateral patch layouts on manifold surfaces. The resulting layouts are c...
TCAD
2002
13 years 5 months ago
2002
This paper describes an application of a Constructive Genetic Algorithm (CGA) to the Gate Matrix Layout Problem (GMLP). The GMLP happens in very large scale integration (VLSI) desi...
VLC
2002
13 years 5 months ago
2002
More powerful personal computers and higher network bandwidth has meant that graphics has become increasingly important on the web. Graph-based diagrams are one of the most import...