347 search results - page 3 / 70 » Caching processor general registers |
ISCA
1991
IEEE
13 years 9 months ago
1991
IEEE
When address reference streams exhibit high degrees of spatial and temporal locality, many of the higher order address lines carry redundant information. By caching the higher ord...
DAC
2004
ACM
14 years 6 months ago
2004
ACM
This paper describes a strategy for verifying data-hazard correctness of out-of-order processors that implement register-renaming. We define a set of predicates to characterize re...
HPCA
2004
IEEE
14 years 6 months ago
2004
IEEE
Data communications between producer instructions and consumer instructions through memory incur extra delays that degrade processor performance. In this paper, we introduce a new...
ISCA
1996
IEEE
13 years 10 months ago
1996
IEEE
Historically, processor accesses to memory-mapped device registers have been marked uncachable to insure their visibility to the device. The ubiquity of snooping cache coherence, ...
EUROPAR
1997
Springer
13 years 10 months ago
1997
Springer
Instruction scheduling in general, and software pipelining in particular face the di cult task of scheduling operations in the presence of uncertain latencies. The largest contrib...