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ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
13 years 9 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
ICCAD
2002
IEEE
141views Hardware» more  ICCAD 2002»
14 years 1 months ago
A hierarchical modeling framework for on-chip communication architectures
— The communication sub-system of complex IC systems is increasingly critical for achieving system performance. Given this, it is important that the on-chip communication archite...
Xinping Zhu, Sharad Malik
EH
2004
IEEE
117views Hardware» more  EH 2004»
13 years 8 months ago
Multi-objective Optimization of a Parameterized VLIW Architecture
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
GIS
2007
ACM
13 years 10 months ago
Cell-based generalization of 3D building groups with outlier management
In this paper, we present a technique that generalizes 3D building groups of virtual 3D city models according to a cell structure that is derived from infrastructure networks. In ...
Tassilo Glander, Jürgen Döllner
ICCAD
2006
IEEE
177views Hardware» more  ICCAD 2006»
14 years 1 months ago
Application-specific customization of parameterized FPGA soft-core processors
Soft-core microprocessors mapped onto field-programmable gate arrays (FPGAs) represent an increasingly common embedded software implementation option. Modern FPGA soft-cores are p...
David Sheldon, Rakesh Kumar, Roman L. Lysecky, Fra...