Sciweavers

44 search results - page 3 / 9
» Cell selection from technology libraries for minimizing powe...
Sort
View
DAC
2008
ACM
14 years 6 months ago
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65nm and below. Voltage waveform shapes are increasingly more difficult to repr...
S. Raja, F. Varadi, Murat R. Becer, Joao Geada
MICRO
2005
IEEE
113views Hardware» more  MICRO 2005»
13 years 11 months ago
Thermal Management of On-Chip Caches Through Power Density Minimization
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I....
ICCAD
1997
IEEE
117views Hardware» more  ICCAD 1997»
13 years 10 months ago
Generalized matching from theory to application
This paper presents a novel approach for post-mapping optimization. We exploit the concept of generalized matching, a technique that nds symbolically all possible matching assignm...
Patrick Vuillod, Luca Benini, Giovanni De Micheli
AIA
2007
13 years 7 months ago
Minimizing leakage: What if every gate could have its individual threshold voltage?
Designers aim at fast but low-power consuming integrated circuits. Since high processing speed always comes with high energy demands, the literature provides several ways to reduc...
Ralf Salomon, Frank Sill, Dirk Timmermann
ICCAD
2001
IEEE
143views Hardware» more  ICCAD 2001»
14 years 2 months ago
Transient Power Management Through High Level Synthesis
The use of nanometer technologies is making it increasingly important to consider transient characteristics of a circuit’s power dissipation (e.g., peak power, and power gradien...
Vijay Raghunathan, Srivaths Ravi, Anand Raghunatha...