28 search results - page 1 / 6 » Challenges in clockgating for a low power ASIC methodology |
ISLPED
1999
ACM
13 years 9 months ago
1999
ACM
Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activiiy in the lo...
CASES
2004
ACM
13 years 10 months ago
2004
ACM
Recognizing speech, gestures, and visual features are important interface capabilities for future embedded mobile systems. Unfortunately, the real-time performance requirements of...
ISLPED
2010
ACM
13 years 5 months ago
2010
ACM
Structured ASICs provide an exciting middle ground between FPGA and ASIC design methodologies. Compared to ASIC, structured ASIC based designs require lower non recurring engineer...
ENTCS
2006
13 years 4 months ago
2006
In recent years several successful GALS realizations have been presented. The core of a GALS system is a locally synchronous island that is designed using industry standard synchr...
DAC
2003
ACM
14 years 5 months ago
2003
ACM
Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best pow...