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DSN
2004
IEEE
13 years 8 months ago
Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline
The progression of implementation technologies into the sub-100 nanometer lithographies renew the importance of understanding and protecting against single-event upsets in digital...
Nicholas J. Wang, Justin Quek, Todd M. Rafacz, San...
FDTC
2011
Springer
267views Cryptology» more  FDTC 2011»
12 years 4 months ago
An In-depth and Black-box Characterization of the Effects of Clock Glitches on 8-bit MCUs
Abstract—The literature about fault analysis typically describes fault injection mechanisms, e.g. glitches and lasers, and cryptanalytic techniques to exploit faults based on som...
Josep Balasch, Benedikt Gierlichs, Ingrid Verbauwh...
MICRO
2007
IEEE
150views Hardware» more  MICRO 2007»
13 years 11 months ago
Leveraging 3D Technology for Improved Reliability
Aggressive technology scaling over the years has helped improve processor performance but has caused a reduction in processor reliability. Shrinking transistor sizes and lower sup...
Niti Madan, Rajeev Balasubramonian
ISPASS
2007
IEEE
13 years 11 months ago
An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures
Semiconductor transient faults (i.e. soft errors) have become an increasingly important threat to microprocessor reliability. Simultaneous multithreaded (SMT) architectures exploi...
Wangyuan Zhang, Xin Fu, Tao Li, José A. B. ...